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When a transition fault test set leaves undetected transition faults because of logic redundancies, test constraints, or the existence of hard-to-detect faults, it leaves transition fault sites uncovered. For the case where multicycle tests are used, this paper explores the possibility of covering the sites of undetected transition faults by using tests for what are referred to as optimistic unspecified transition faults. For this discussion, a standard transition fault is associated with an extra delay of a single clock cycle. An unspecified transition fault captures in a single fault the behaviors of transition faults of different durations. Because faults with different durations may be detectable or undetectable independently by a multicycle test, an unspecified transition fault may be detected even if the standard transition fault at the same site is undetectable. This effect is enhanced with optimistic unspecified transition faults. The paper describes an iterative test compaction procedure for multicycle tests that supplements the set of standard transition faults with optimistic unspecified transition faults to cover the sites of undetected standard transition faults. 

Gate-exhaustive and cell-aware tests are generated based on input patterns of cells in a design. While the tests provide thorough testing of the cells, the interconnects between them are tested only as input and output lines of cells. This paper defines cell-based faults that allow the interconnects to be tested more thoroughly within a uniform framework that only targets input patterns of cells. In contrast to a real cell that is part of the design, a dummy cell is used for defining interconnect-aware faults. Using a gate-level description of the circuit, a dummy cell contains an interconnect, an output gate of the real cell that drives it, and an input gate of the real cell that it drives. Experimental results for benchmark circuits show that many of the interconnect-aware faults are not detected accidentally by gate-exhaustive tests, and that the quality of the test set is improved by targeting interconnect-aware faults. Here, quality is measured by the numbers of detections of single stuck-at faults in a gate-level representation of the circuit. 

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. The paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, the paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. The paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes.